(1) Field of the Invention
The present invention relates to a data processing configuration with a circuit configuration that connects a first communication bus with a second communication bus, wherein a second circuit configuration is also connected with the first communication bus,
(2) Description of Related Art
Data processing devices comprise various units such as the CPU (central processing unit), memory, display, hard disk controller etc., which are connected with each other through communication buses and exchange data. Often several different communication buses are arranged in a data processing device, which differ from each other in their transmission speed, bus architecture, universality and/or specialization.
In order to connect a first communication bus with a second communication bus, a so-called bridge is generally used. The bridge can serve e.g. as bus master for one of the communication buses. This means that the bridge allocates read and write rights on the bus to the remaining components of this communication bus that are connected.
For example, based on the specific protocol of a communication bus, read and write access is always set for the duration of two clock pulses of a timing signal. In the first clock pulse, the address and cycle information is made available, while in the second clock pulse data is transmitted, with the address and cycle information remaining stable. Problems arise from this rigid bus protocol when the data is not made available by the component that is connected to the communication bus within two clock cycles. A solution to this problem has so far been enabled by connecting the non-bus conforming module to another bus. This solution, however, requires additional development efforts because in this case a special interface must be developed for each module. Another possibility to solve this problem consists of modifying the bridge in such a way that in dependence on the selected address a previously established number of clock cycles is allowed to pass until the data is read. The disadvantage here is first the fact that the number of clock cycles that have be allowed to pass is fixed and cannot be adjusted to changing circumstances. The second disadvantage is the fact that the bridge must be adjusted separately to each peripheral module, which limits the re-use of the bridge drastically.